The desire for integrated circuits of greater complexity and performance has driven designers to shrink the size of minimum features in the horizontal plane. Avoidance of excessive current density, however, has meant that the horizontal scaling has not necessarily been accompanied by a reduction in the vertical dimension. This has resulted in increase of the ratio of feature height to feature width, something generally referred to as aspect ratio. The increased aspect ratio has resulted in problems with the use of conventional single-layer resists in integrated circuitry fabrication. Multilevel resist processes have been developed to overcome these problems.
Multilevel resist processing is a lithography method (not necessarily photolithography) whereby a thick base layer (not necessarily a photosensitive layer) is covered with one or more thinner layers, the top one of which is a sensitive film at the wavelength of light or other exposure energy to be used. The thick base layer is typically an organic layer which is spun onto the wafer and may be thicker than the underlying steps to provide an outer surface which is smooth and generally planar. If the underlaying layer over which the base layer is provided is not already planar, the base layer is typically intended to provide a significantly more planar outer surface than the original wafer topography. An example thickness for the base layer is 1 micron.
After baking this bottom layer, a thinner imaging layer is provided thereover. In certain instances, a thin intermediate masking layer, such as SiO.sub.2, is deposited on the thick layer prior to depositing the imaging layer. High resolution patterns are then created in the thin top layer through openings in a mask utilizing incident energy capable of changing properties of the exposed portions of the outer layer. In positive imaging using a positive imaging layer, the transformed regions of the thin top layer are then removed. The removed portions are next precisely transferred into the underlying layers, including the thick planarizing layer, using the delineated imaging layer as a blanket exposure or etching mask to pattern the base or planarizing layer. Example preferred prior art methods include reactive ion etching utilizing an oxygen-containing gas in a high density plasma etcher for the base layer. For the intermediate masking layer, an example etching chemistry is a fluorocarbon/hydrofluorocarbon gas mix.
Multilevel resist technology has not gained significant popularity due to the added complexity and cost compared to standard lithography/resist combinations using a single layer of resist. Yet there are at least two reasons that may make the use of multilevel resist technologies for patterning substrates more desirable in the future.
First, shorter and shorter wavelengths when the resist layer is photoresist are being utilized to achieve better resolution. Unavailability of appropriate single layer resists for the wavelength of interest may prevent use of single layer resist. For example, production wavelengths below 200 nanometers may fundamentally require use of multilevel resist technology. Second, multilayer resist technology may be utilized to extend the useful life of current lithography tools by decreasing the imaging layer thickness. This would be highly desirable to avoid or delay incurring the very high cost of purchasing new lithography technology and equipment.
This invention was principally motivated in improving attributes in the intermediate masking layer formed between the base or bottom layer and the imaging layer.